Vesper is a leader in the high growth MEMS microphone market. Using our cutting-edge proprietary piezoelectric MEMS technology, we have pioneered a new class of voice interface devices. Vesper has a fun and energetic startup culture, and we are well funded by leading VCs such as Accomplice and Amazon’s Alexa Fund, plus we have partnered with leading companies such as DSP Group, Synaptics, GLOBALFOUNDRIES and TSMC.
We seek experienced candidates for this IC Layout Engineering position. The IC Layout Engineer will be responsible for all technical aspects of the layout of ASICs designed for Vesper’s microphones. Floorplanning, layout of analog and digital designs in 180nm or lower nodes process. Top level layout lead for the ICs developed by the design team.
This position reports to the VP of Engineering ASIC and will be based in downtown Boston.
Qualifications – Required:
- Associate degree or BS of Engineering – Layout design or equivalent.
- 10 to 15 years of IC layout experience for analog and digital designs. Multiple tapeouts track record of complex mixed signal ICs.
- Experience working with Cadence and Mentor design tools.
- Experience with leading the top-level integration of analog ICs with some small embedded digital designs.
- Experience with digital auto place and route tools for small to medium sized designs.
- Experience with process nodes 180nm or lower.
- Able to develop accurate and detailed schedules and deliver to them.
- Willing to work in Downtown Boston.
Qualifications – Desired:
- Experience in interfacing with foundries to handle all aspects of tapeouts.
- Experience with ICmanage and Perforce. Able to support CAD activities if needed.
- Strong knowledge of analog design and principles.
- Experience in Audio, ADCs/DACs, MEMs ASICs layouts preferred.
Candidates must be authorized to work in the United States
Wage: Vesper offers a competitive salary and an attractive stock option package