Title: Senior IC Layout Design Engineer
Reports to: Director of ASIC Design
Location: Boston, MA
Vesper is the leader in the high growth MEMS microphone market. Using our cutting-edge proprietary piezoelectric MEMS technology, we have pioneered a new class of voice interface devices. Vesper has a fun and energetic startup culture, and we are well funded by leading VCs such as Accomplice and Amazon’s Alexa Fund, plus we have partnered with leading companies such as DSP Group, Synaptics, GLOBALFOUNDRIES and TSMC.
We are seeking experienced candidates for the role of Senior Layout Design Engineer to join our ASIC team. This is a contract to a hire position.
The senior layout design engineer will lead the layout design work in the ASIC team, contribute at every level of layout, from transistor level layout of sensitive circuits, to full chip floor planning, top-level interconnects and verification. We design low-noise sensor front-ends, ADCs, power conditioning and more.
- 7+ years of experience in CMOS analog/mixed-signal layout
- Knowledge of best practice layout techniques for analog circuits. Excellent understanding of device matching and parasitics
- Experience with integration of block level layouts for ASICs, full chip DRC and LVS and releasing layouts for fabrication
- Mastery of Cadence Virtuoso Layout XL
- Experience with Virtuoso Layout GXL and EXL features
- Scripting and automation to increase productivity
- Place and Route of small to medium digital blocks
- Self-starter with initiative and independent judgment
- Excellent communication, planning and organizational skills
- Ability to prioritize and handle multiple tasks at a time
Candidates must be authorized to work in the United States
Wage: This is a contract to a hire position. Vesper offers a competitive salary, benefits and attractive stock option package
Submit CV or resume to: email@example.com